1G to 1,000G Interlaken ILK & ILA IP Core

Lowest latency

We do not believe there is a lower latency solution in the market, and many customers are asking for it today. Here are some examples.

12x10G core latency (no serdes) 50nS in FPGA
12x10G core latency (no serdes) 13nS in 28nM ASIC

Lowest gate count

Saving gates is always a benefit, and we are typically 3-4x smaller in gate count than most implementations. This can make a huge impact on ASIC die area or FPGA cost.

Huge timing margin

Often our cores will run in the slowest speed grade saving money, and compile with push button ease in minutes, significantly reducing development time by reducing time between iterations.

Single code base delivered as source code

We deliver one code base, as machine readable source. You can generate any version you desire and use internally for any what if scenarios you wish to try. You only buy a license for the specific configuration you decide to move forward with.

If a future need for another core appears, with the universal source already in house, any core can be generated at will and no re-learning is required as it is the same core.

—Fully Parameterized Solution
  • —Configurable System Bus Width
  • —Configurable Core Bus Width
  • —Configurable Lane Count
Same core supports ILA and ILK
  • Not does the same core support support both modes but each sequential packet could support different modes
—Enhanced Scheduling support
  • Supports enhanced scheduling support
—Support Altera, Xilinx, Microsemi, Achronix FPGA’s, and all ASIC nodes
—Size efficient
The core is built with efficiency in mind. Here are typical resource utilizations for the core:
  • —ILA/K-4x10G, soft MAC+PCS; ~10K LUTs
  • —ILA/K-12x10G, soft MAC+PCS; ~28K LUTs
—Low Latency
  • 12x10G core latency (no serdes) 50nS in FPGA
  • 12x10G core latency (no serdes) 13nS in 28nM ASIC
—Scalability
  • —1 lane to 32 lanes, up to 1,000Gbps bandwidth
—Timing Margin
  • —Compiles at 500+ MHz in FPGA
—Compliant
—The core is compliant with:
  • Interlaken Protocol Specification v1.2
  • —Interlaken Look-Aside Protocol Specification v1.1
—Compile-Time Parameters
  • —Lane Count
  • —System Bus Width
  • —Core Bus Width
  • —Flow Control Count
  • —Channel Count
—Runtime Configurable
  • —Mode; ILA, ILK or both
  • —Packet Mode or Segment Mode
  • —BurstShort, BurstMin, BurstMax
  • —Enhanced Scheduling
  • —Active Flow Control Count
  • —Active Lane Count & Single Bad lane
  • —Meta-frame Size
  • —Loopback
  • —PRBS

—Verification – Full third party verification complete, for details contact us

—Availability – Now

—Deliverables – Verilog RTL, Data Sheet, Product Brief, Bring up guide, Test benches
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To learn more about the product contact us.
Tamba offers industry's lowest latency, power, and size solution for the Interlaken communication protocol. The Universal Interlaken IP Core can be customized from 1 Gbps to 1,000 Gbps and targeted to both FPGA and ASIC platforms. The extensively pipe-lined architecture can be seamlessly ported from the FPGA to ASIC platform with drastic reductions in latency, power consumption, and logic size. Interlaken is a high-speed chip-to-chip connectivity protocol optimized for high bandwidth and reliable packet transfers using a minimum number of pins. Tamba’s Universal Interlaken IP Core is customizable to any data rate from 1 to 600 Gbps. The primary benefit of the core is that it facilitates transmission of large amounts of data within a system with minimum overhead. The high-speed data transfer between components is accomplished using state-of-the-art serial-link (Serializer/Deserializer) technologies. The Interlaken protocol can manage reliable packet transfer at speeds of up to 6 Gbps per lane (pin pair). A numbers of serial lanes can be bundled together to create an Interlaken interface to transfer data up to 600 Gbps and beyond. An innovative feature of the Tamba Interlaken IP Core is highly efficient implementation of CRC-32 (Cyclical Redundancy Check) algorithm for reliable transmission of data. Tamba’s CRC-32 Core consumes a minimum amount of logic in both ASICs and FPGAs.